Embodiments of the present inventive concept relate generally to image sensors, and more particularly to image sensors capable of compensating a fixed pattern noise output through each column in the image sensor. Embodiments of the inventive concept also relate to image processing systems including this type of image sensor.
Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) must convert an analog signal generated by an active pixel sensor (APS) array into a corresponding digital signal. This is usually accomplished by use of an analog to digital converter (ADC). Thus, a CMOS image sensor will operate, depending upon the image resolution required, according to one class of methods that use a single ADC or another class of methods that use a so-called column ADC. The column ADC is essentially an ADC having a relatively simple structure that may be embodied in each column of a CMOS image sensor. The column ADC has the advantage of consuming relatively less power even with a large chip area. Signal conversion methods associated with the column ADC may perform correlated double sampling (CDS) on an analog output voltage which is a pixel output signal, store the resulting voltage, and provide a comparison result for digital code generation by comparing the voltage stored by the CDS operation with a predetermined reference voltage (e.g., a ramp signal generated by a ramp generator).
In response to continuing demands for high resolution, certain high resolution and very densely integrated CIS have been developed. The unit pixel sizes of these high resolution CIS are so small that manufacturing yields may become negatively motivated. That is, as unit pixel size decreases, image quality may actually deteriorate due to, for example, noise issues associated with the pixel power supply circuitry. Decreasing unit pixel size therefore tends to increase the number of defective CIS identified during post-manufacturing screening. Of course, the identification of a defective CIS is a matter of degree, and various compensation schemes have been proposed to mitigate image quality deterioration.
Moreover, since an ADC capacitor of defined minimum area is often used in conventional ADC conversion methods, problems associated with so-called column fixed pattern noise (CFPN) may arise due to the resulting decrease in capacitance provided by the ADC capacitor, as well as impedance mismatching in each column of the ADC.